materi kuliah teknik : komponen mikrokontroler

Bagian-bagian mikrocontroler

·         Flash adalah suatu jenis Read Only Memory yang biasanya diisi dengan program hasil buatan manusia yang harus dijalankan oleh mikrokontroler

·         RAM (Random Acces Memory) merupakan memori yang membantu CPU untuk penyimpanan data sementara dan pengolahan data ketika program sedang running

·         EEPROM  (Electrically Erasable Programmable Read Only Memory) adalah memori untuk penyimpanan data secara permanen oleh program yang sedang running

·         Pin I/O adalah kaki untuk jalur keluar atau masuk sinyal sebagai hasil keluaran ataupun masukan bagi program

·         Timer adalah modul dalam hardware yang bekerja untuk menghitung waktu/pulsa 

·         UART (Universal Asynchronous Receive Transmit) adalah jalur komunikasi data khusus secara serial asynchronous

·         SPI (Serial Peripheral Interface) adalah jalur komunikasi data khusus secara serial secara serial synchronous

·         ISP (In System Programming) adalah kemampuan khusus mikrokontroler untuk dapat diprogram langsung dalam sistem rangkaiannya dengan membutuhkan jumlah pin yang minimal 

DMA to PLB 4 Controller

DMA to PLB4 Controller
This DMA controller provides a DMA interface dedicated to the USB 2.0 device ports and the 128-bit PLB.
Features include:
• 4 independent channels supporting internal USB 2.0 Device endpoints 1 and 2
• Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers
• Scatter/gather capability
• 128-byte buffer with programmable thresholds
Serial Ports (UART)
Features include:

External Peripheral Bus Controller (EBC) The PowerPC 440 EP

External Peripheral Bus Controller (EBC)
Features include:
• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation
• Burst and non-burst devices
• 16-bit byte-addressable data bus
• 30-bit address
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
– 256 Wait States for non-burst

PCI Interface of The PowerPC 440 EP

PCI Interface
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
• PowerPC CoreConnect Bus (PLB) Specification Version 3.1
• PCI Specification Version 2.2
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• PCI 2.2
– Frequency to 66MHz
– 32-bit bus
• PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
• Support for Message Signaled Interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four
256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
• Registered and non-registered industry standard discrete devices
• 32-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 1.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• DDR200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)

microprocessor: 440EP PowerPC 440EP Embedded Processor

PowerPC® 440 processor core operating up to
667MHz with 32KB I-cache and D-cache with
parity checking.
• Selectable processor:bus clock ratios of N:1, N:2.
• Floating Point Unit with single- and doubleprecision
and single-cycle throughput.
• Dual bridged Processor Local Buses (PLBs) with
64- and 128-bit widths.
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) interface operating up to 133MHz with
ECC.
• DMA support for external peripherals, internal
UART and memory.
• PCI V2.2 interface (3.3V only). Thirty-two bits at
up to 66MHz.
• Programmable interrupt controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT).
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are MII,
RMII, and SMII with packet reject.

MPC7448 POWERPC PROCESSOR HIGHLIGHTS mikroprosesor

The MPC7448 is the first discrete high- MPC7448 POWERPC® PROCESSOR BLOCK DIAGRAM
performance PowerPC® processor manufactured on 90 nanometer silicon-on-insulator (SOI)
process technology and continues Freescale Semiconductor’s strong legacy of providing PowerPC products with significant processing performance at very low power. The MPC7448 is designed to exceed 1.5 GHz processing performance and offers enhanced power management capabilities. Running at 1.4 GHz, the MPC7448 is expected to use less than 10 watts of power. MPC7448 processors are ideal for leading-edge computing, embedded network control and signal processing applications. Key architectural features include an MPX bus that scales to 200 MHz, 1 MB of on-chip L2 cache with support for Error Correcting Codes (ECC), and full 128-bit implementation of Freescale’s AltiVec™ technology with the added feature of supporting out-of-order transactions. The MPC7448 is pin compatible with Freescale’s MPC7447 and MPC7447A PowerPC products, offering an easy upgrade path to better system performance. Caching In
L2 cache helps keep the PowerPC processor pipeline full, enabling faster and more efficient processing—and the increase in the MPC7448’s L2 cache to 1 MB provides even greater opportunity for performance gains.